When you generate the DDR4 IP in Vivado, you face a daunting wizard. Here is how to configure it for success.
—DDR4, FPGA, Xilinx, MIG, memory controller, high-bandwidth, UltraScale+ xilinx ddr4 ip
Features write leveling, read/write VREF calibration, and per-bit deskew. Protocol Features: Burst Support: Standard 8-word burst support. Efficiency: When you generate the DDR4 IP in Vivado,