write_verilog -force ./outputs/post_synth_netlist.v write_vhdl -force ./outputs/post_synth_netlist.vhd
16GB is the bare minimum for small designs; 32GB to 64GB is recommended for Kintex or Virtex UltraScale+ projects. xilinx vivado 2020.2
If you face routing congestion, 2020.2 introduced a "Congestion Map" in the Device View. Use this to identify high-fanout nets that are choking your slice resources. Why Use 2020.2 Today? write_verilog -force
After synthesis completes: